If a system requests for a resource, it will need to wait for that resource to become available before it can continue.
There are two methods to wait for resource availability - synchronous waiting (polling) and asynchronous waiting (interrupts)
Every x time interval, the software will query the I/O device to see if it available.
Whilst no extra hardware is required (polling is software-based), it is not efficient due to wasted time checking for the I/O.
A Programmable Interrupt Controller (PIC) inside the CPU listens for signals from the I/O devices, and causes the CPU to pause its operation and handle the ‘interrupt event’.
The PIC works alongside the rest of the CPU to perform the following three tasks
When an Interrupt Request (IRQ) is received by the PIC, the Interrupt Vector Table (IVT) is accessed to find the relevant Interrupt Service Routine (ISR) to execute.
The ISR is the function that is executed which handles the interrupt
When an interrupt is received, it takes a little while to transfer CPU execution control to the ISR. This delay is known as the interrupt latency, and is roughly 5 clock cycles - to save the return address, registers, and to jump to the ISR
If multiple interrupts are received at the same time, which one is handled first???
Daisy-Chain Priority Resolution
INTA) signal from the CPU will only pass the INTA signal to the next device when it has finished.Separate IRQ bus lines
IRQ0 > IRQ1 > IRQ2 > ...It is favourable to prevent other interrupts from being executed until the previous ISR is complete. There are two methods to achieve this.