Assignment One

Untitled picture.png Machine generated alternative text: The circuit in figure l, with can be configured for a variety of applications by the appropriate connection of terminals A, B, C, D, and O. Untitled picture.png Figure 1 Untitled picture.png a) Show how the circuit can be used to implement a difference amplifier of unity gain. [10 Marks]            
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Untitled picture.png b) Show how the circuit can be used to implement single-ended amplifiers with gains: (i) -1; (ii) +1; (iii) +2; (W) +1/2. In the implementation avoid from leaving a terminal open-circuited for such a terminal may act as an "antenna" picking up interference and noise through capacitive coupling. When more than one circuit implementation is possible, comment on the relative merits of each from matching and input resistance point of [20 marks] Untitled picture.png Machine generated alternative text: Untitled picture.png Machine generated alternative text: Ink Drawings Untitled picture.png Machine generated alternative text: Ink Drawings Untitled picture.png Machine generated alternative text: Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings         Ink Drawings Ink Drawings Ink Drawings Ink Drawings    Ink Drawings Ink Drawings Ink Drawings Ink Drawings                  
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c) In estimating DC imperfections (input offset voltage, input offset current and the bias current) of an op-map, an inverting amplifier with nominal gain Of -100 using 100kQ and resistors is implemented using the op-amp as shown in Fig 2(a) below.

 

 

Rz=10MO RÉIOMO Figure 2(b): Modified inverting amplifier

 

 Rz=10MQ Figure 2(a): Inverting amplifier

 

Untitled picture.png Measurements are conducted on the output voltage of the inverting amplifier under the following conditions: (i) the input (VD is open circuited and the output voltage is found to be +9.31 V ; (ii) the input (Vi) is grounded and the Output voltage is found to be +9.09V; (iii) the inverting amplifier is further modified by connecting a IOMQ resistor between the positive input terminal and ground (shown in Figure 2(b)) and the output voltage is measured to be -0.8V with the input (VD opened. What are the estimate values of the input offset voltage, input offset current and input bias current Of the op-amp? [30 Marks] Ink Drawings Ink Drawings Ink Drawings
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Untitled picture.png Machine generated alternative text: R2=10MO R3=10MO Figure 2(b): Modified inverting amplifier 
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Untitled picture.png Machine generated alternative text: R2=10MO R3=10MO Figure 2(b): Modified inverting amplifier Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings Ink Drawings                   
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Untitled picture.png Machine generated alternative text: e) In reference to figure l, the op-amp is configured as an inverting amplifier. The large signal limitations and other characteristics of the op-amp are provided as in table l. The DC imperfections are as estimated above. The values of resistors used in the inverting amplifier configuration are Rl=lkQ, R3=lkQ, R4=lOkQ. Lar e si al limitations Ou ut volta saturation Ou ut current limits Slew rate ±13V +20mA 0.5V/gs Other characteristics Internal com nsation ca acitor 3 F n 100 volta e ain n 100 bandwidth IOOdB 6Hz Table 1: The non-ideal op-amp characteristics  
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Machine generated alternative text: Estimate the bandwidth of the amplifier assuming that the internal compensation capacitor creates the dominant pole in the frequency response of the op-amp? [6 marks]
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Machine generated alternative text: 11. With Vin = and VA=IV , will there be a frequency at which the output (v o) will be distorted? If so, what is that frequency? [7 marks]

                   

Machine generated alternative text: 111. With Vin = VAcos(2a1000t) where VA=IV and assuming that a resistive load is connected at the output between node Vo and ground, what is the constrain on the resistive load if the output is to be undistorted? [7 marks]
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